The present invention relates to the field of semiconductor devices and their manufacture. More specifically, in one embodiment the invention provides bipolar devices on a substrate and a process for their fabrication.
Bipolar semiconductor devices and their methods of manufacture are well known. Such devices are described in, for example, U.S. Pat. No. 4,609,568 (Koh et al.) and U.S. Pat. No. 4,764,480 (Vora), both assigned to the assignee of the present invention and incorporated herein by reference for all purposes.
Recently, the advantages of bipolar and CMOS devices have been beneficially incorporated into circuits using both types of devices on a single substrate. Circuits which incorporate both bipolar and CMOS devices have come to be known as "BiCMOS." BiCMOS devices offer the advantages of the high packing density and low power consumption of CMOS devices, as well as the high speed of bipolar devices. One BiCMOS device and process for fabrication thereof is described in U.S. Pat. No. 4,764,480.
Isolation of bipolar junction transistors ("BJTs") is an important step in bipolar and BiCMOS fabrication. One well-known isolation method is the so called side-walled-masked-isolation (SWAMI) process. BJTs fabricated according to this and some related processes may have a "walled emitter" in which the emitter of the transistor intersects the isolation oxide. Walled emitter devices make effective use of the device active area, minimizing the parasitic collector-base capacitance for a given emitter area. Further, transistors with walled emitters generally require reduced amounts of layout area per transistor. For comparison, in a non-walled emitter BJT, the emitter is separated from the isolation oxide, and the resultant structure has a generally uniform emitter-base edge profile on all edges. This type of transistor usually requires more layout area for a given lithography technique than a walled emitter BJT.
Walled emitters can have certain problems, among which are excessive collector-emitter leakage currents ("I.sub.CEO ") and lower the collector-emitter breakdown voltage, BV.sub.CEO. I.sub.CEO is a current that flows between the collector and emitter when a voltage is placed between the collector and emitter while the base terminal is left open. Substantial leakage currents can reduce yield and/or cause improper circuit operation.
I.sub.CEO can be excessive due to a number of factors. Some of these are mediated by excessive isolation oxide encroachment at the corners of the active areas on the BJT. For example, the intrinsic base dopant can segregate into the field oxide adjacent the base, leading to locally lower based dopant concentrations. This can also allow the subsequently formed emitter region to penetrate further into the intrinsic base region, resulting in a reduced base width. Both effects (reduced base width and lower base dopant concentration) can lead to excessive leakage current between the emitter and the collector at the intersection of the intrinsic base and the isolation oxide. In addition, charges present in the field oxide as a result of dopant segregation can cause an inversion of the P-type intrinsic base region at the edge of the walled emitter, creating a leakage path between the collector and emitter.
One recently developed method for off-setting the above problems involves forming diffusion compensation regions in the areas where the base width narrowing occurs. The diffusion compensation regions contain elevated concentrations of the base dopant so that the dopant segregation or inversion of the intrinsic base region is avoided. Typically the diffusion compensation regions are formed by implanting and diffusing base dopant into the isolation oxide regions before the isolation oxide is grown. Devices formed according to this process are described in U.S. patent application Ser. No. 07/821,256 which is incorporated herein by reference for all purposes.
Other methods for reducing or controlling I.sub.CEO leakage in walled emitters have generally tended to reduce the performance of the BJTs. For example, increasing the base width or increasing the dopant concentration throughout the base region reduce the performance of the BJT by increasing the transit time of charges in the base region and by increasing the parasitic capacitances of the BJTs.
From the above it is seen that an improved method for controlling I.sub.CEO currents in a BJT having a walled emitter (particularly for use in BiCMOS devices) is desired to provide devices with improved performance.